v_exp_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_exp_f32

Calculate 2 raised to the power of the single-precision float input and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
0100101
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 37 in OP rebuilds 0x7E004A00, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD CDNA 4 (opcode 32, field layout), AMD CDNA 3 (opcode 32, field layout), AMD CDNA 2 (opcode 32, field layout), AMD CDNA 1 (opcode 32, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (field layout), AMD RDNA 1 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 37
Identifier 0x7E004A00

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

1ULP accuracy, denormals are flushed.

Related PTX Concepts

2^x (Base-2 Exponential) ↗
equivalent with restrictions
ex2 (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f32 = pow(2.0F, S0.f32)

Example

V_EXP_F32(0xff800000) => 0x00000000     // exp(-INF) = 0
V_EXP_F32(0x80000000) => 0x3f800000     // exp(-0.0) = 1
V_EXP_F32(0x7f800000) => 0x7f800000     // exp(+INF) = +INF

Reproduced from AMD's official "AMD Instinct MI300" ISA Reference Guide for technical accuracy.

Sources