v_dual_max_num_f64 GPU Native ISA AMD Vector

Vector Arithmetic

v_dual_max_num_f64

Select the IEEE maximumNumber() of two double-precision float inputs and store the selected value into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOPD) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOPD

Operands

  • VDSTX
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)
  • SRCX0
    Read. Simple operands. Covers all operands that are allowed as scalar or vector sources except SRC_LITERAL and SRC_LITERAL64. Data format: 64-bit double-precision floating point value. (OPR_SRC_SIMPLE, FMT_NUM_F64)
  • VSRCX1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 64-bit double-precision floating point value. (OPR_VGPR, FMT_NUM_F64)

In AMD's order, as its machine-readable ISA specification lists them for the VOPD3XY encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Sources