v_dot2_f16_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_dot2_f16_f16

Compute the dot product of two packed 2-D half-precision float inputs, add the third input and store the result into a vector register.

Encoding

Binary Layout (AMD RDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1001100110
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD RDNA 4). Opcode 614 in OP rebuilds 0x00000000D6660000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout).

Format VOP3
Width 64 bits
Opcode 614
Identifier 0x00000000D6660000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit half-precision floating point value. (OPR_VGPR, FMT_NUM_F16)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_F16)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. Packed 2-component value. (OPR_SRC, FMT_NUM_PK2_F16)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. (OPR_SRC, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD RDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_dot2_f16_f16 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources