v_cvt_sr_f16_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_sr_f16_f32

Convert from a single-precision float input to a half-precision value with stochastic rounding using seed data from the second input.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
1010100110
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 678 in OP rebuilds 0x00000000D2A60000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3
Width 64 bits
Opcode 678
Identifier 0x00000000D2A60000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F16)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_F32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a single-precision float input to a half-precision value with stochastic rounding using seed data from the second input. Store the result into 16 bits of a vector register using OPSEL to determine which word of the destination to overwrite.

Sources