v_dot2c_f32_bf16 GPU Native ISA AMD Vector

Vector Arithmetic

v_dot2c_f32_bf16

Compute the dot product of two packed 2-D BF16 float inputs in the single-precision float domain and accumulate with the single-precision float value…

Encoding

Binary Layout (AMD CDNA 4)
0
31
010110
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 22 in OP rebuilds 0x2C000000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP2
Width 32 bits
Opcode 22
Identifier 0x2C000000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_PK2_BF16)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_PK2_BF16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Compute the dot product of two packed 2-D BF16 float inputs in the single-precision float domain and accumulate with the single-precision float value in the destination register.

Example

v_dot2c_f32_bf16 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx950_xdlops.s). Not from an AMD document, and not authored here.

Sources