v_dot2c_f32_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_dot2c_f32_f16

Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate with the single-precision…

Also written as v_dot2acc_f32_f16. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
0
31
110111
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 55 in OP rebuilds 0x6E000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 2). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP2
Width 32 bits
Opcode 55
Identifier 0x6E000000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_PK2_F16)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_PK2_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Compute the dot product of two packed 2-D half-precision float inputs in the single-precision float domain and accumulate with the single-precision float value in the destination register.

Semantics

tmp = D0.f32; tmp += f16_to_f32(S0[15 : 0].f16) * f16_to_f32(S1[15 : 0].f16); tmp += f16_to_f32(S0[31 : 16].f16) * f16_to_f32(S1[31 : 16].f16); D0.f32 = tmp

Example

v_dot2c_f32_f16 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources