v_dot8c_i32_i4 GPU Native ISA AMD Vector

Vector Arithmetic

v_dot8c_i32_i4

Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit…

Encoding

Binary Layout (AMD CDNA 4)
0
31
111010
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 58 in OP rebuilds 0x74000000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP2
Width 32 bits
Opcode 58
Identifier 0x74000000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_PK8_I4)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_PK8_I4)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit integer value in the destination register.

Semantics

tmp = D0.i32; tmp += i4_to_i32(S0[3 : 0].i4) * i4_to_i32(S1[3 : 0].i4); tmp += i4_to_i32(S0[7 : 4].i4) * i4_to_i32(S1[7 : 4].i4); tmp += i4_to_i32(S0[11 : 8].i4) * i4_to_i32(S1[11 : 8].i4); tmp += i4_to_i32(S0[15 : 12].i4) * i4_to_i32(S1[15 : 12].i4); tmp += i4_to_i32(S0[19 : 16].i4) * i4_to_i32(S1[19 : 16].i4); tmp += i4_to_i32(S0[23 : 20].i4) * i4_to_i32(S1[23 : 20].i4); tmp += i4_to_i32(S0[27 : 24].i4) * i4_to_i32(S1[27 : 24].i4); tmp += i4_to_i32(S0[31 : 28].i4) * i4_to_i32(S1[31 : 28].i4); D0.i32 = tmp

Example

v_dot8c_i32_i4 v5, v1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (xdl-insts-gfx908.s). Not from an AMD document, and not authored here.

Sources