v_dot8c_i32_i4 GPU Native ISA AMD Vector

V DOT8C I32 I4 Vector Arithmetic

v_dot8c_i32_i4

Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Compute the dot product of two packed 8-D signed 4-bit integer inputs in the signed 32-bit integer domain and accumulate with the signed 32-bit integer value in the destination register.

Semantics

tmp = D0.i32; tmp += i4_to_i32(S0[3 : 0].i4) * i4_to_i32(S1[3 : 0].i4); tmp += i4_to_i32(S0[7 : 4].i4) * i4_to_i32(S1[7 : 4].i4); tmp += i4_to_i32(S0[11 : 8].i4) * i4_to_i32(S1[11 : 8].i4); tmp += i4_to_i32(S0[15 : 12].i4) * i4_to_i32(S1[15 : 12].i4); tmp += i4_to_i32(S0[19 : 16].i4) * i4_to_i32(S1[19 : 16].i4); tmp += i4_to_i32(S0[23 : 20].i4) * i4_to_i32(S1[23 : 20].i4); tmp += i4_to_i32(S0[27 : 24].i4) * i4_to_i32(S1[27 : 24].i4); tmp += i4_to_i32(S0[31 : 28].i4) * i4_to_i32(S1[31 : 28].i4); D0.i32 = tmp

Sources