v_cvt_u32_f64 GPU Native ISA AMD Vector

V CVT U32 F64 Vector Arithmetic

v_cvt_u32_f64

Convert from a double-precision float input to an unsigned 32-bit integer value and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

0.5ULP accuracy, out-of-range floating point values (including infinity) saturate. NAN is converted to 0. Generation of the INEXACT exception is controlled by the CLAMP bit. INEXACT exceptions are enabled for this conversion iff CLAMP == 1.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.u32 = f64_to_u32(S0.f64)

Example

v_cvt_u32_f64 v5, -1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources