v_cvt_sr_bf8_f32 GPU Native ISA AMD Vector

V CVT SR BF8 F32 Vector Arithmetic

v_cvt_sr_bf8_f32

Convert from a single-precision float input to a BF8 value with stochastic rounding using seed data from the second input.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Stochastic rounding. Ignores OMOD and clamp.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a single-precision float input to a BF8 value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL to determine which byte of the destination to overwrite.

Semantics

prev_mode = ROUND_MODE; ROUND_MODE = ROUND_NEAREST_EVEN; s = sign(S0.f32); e = exponent(S0.f32); m = 23'U(32'U(23'B(mantissa(S0.f32))) + S1[31 : 11].u32); tmp = float32(s, e, m); // Add stochastic value to mantissa, wrap around on overflow if OPSEL[3 : 2].u2 == 2'0U then VGPR[laneId][VDST.u32][7 : 0].bf8 = f32_to_bf8(tmp.f32) elsif OPSEL[3 : 2].u2 == 2'1U then VGPR[laneId][VDST.u32][15 : 8].bf8 = f32_to_bf8(tmp.f32) elsif OPSEL[3 : 2].u2 == 2'2U then VGPR[laneId][VDST.u32][23 : 16].bf8 = f32_to_bf8(tmp.f32) else VGPR[laneId][VDST.u32][31 : 24].bf8 = f32_to_bf8(tmp.f32) endif; // Unwritten bytes of D are preserved. ROUND_MODE = prev_mode

Sources