v_div_fixup_legacy_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_div_fixup_legacy_f16

Half precision division fixup. Has non-standard rule for OPSEL.

Encoding

Binary Layout (AMD CDNA 4)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
0111101111
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 495 in OP rebuilds 0x00000000D1EF0000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP3
Width 64 bits
Opcode 495
Identifier 0x00000000D1EF0000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F16)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC_NOLIT, FMT_NUM_F16)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_F16)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_SIMPLE, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

S0 = Quotient, S1 = Denominator, S2 = Numerator. Given a numerator, denominator, and quotient from a divide, this opcode detects and applies specific case numerics, touching up the quotient if necessary. This opcode also generates invalid, denorm and divide by zero exceptions caused by the division. sign_out = (sign(S1.f16) ^ sign(S2.f16)); if isNAN(64'F(S2.f16)) then tmp = cvtToQuietNAN(64'F(S2.f16)) elsif isNAN(64'F(S1.f16)) then tmp = cvtToQuietNAN(64'F(S1.f16)) elsif ((64'F(S1.f16) == 0.0) && (64'F(S2.f16) == 0.0)) then // 0/0 tmp = 16'F(0xfe00) elsif ((64'F(abs(S1.f16)) == +INF) && (64'F(abs(S2.f16)) == +INF)) then // inf/inf tmp = 16'F(0xfe00) elsif ((64'F(S1.f16) == 0.0) || (64'F(abs(S2.f16)) == +INF)) then // x/0, or inf/y tmp = sign_out ? -INF : +INF elsif ((64'F(abs(S1.f16)) == +INF) || (64'F(S2.f16) == 0.0)) then // x/inf, 0/y tmp = sign_out ? -0.0 : 0.0 else tmp = sign_out ? -abs(S0.f16) : abs(S0.f16) endif; if OPSEL.u4[3] then D0 = { tmp.f16, D0[15 : 0] } else D0 = { 16'0, tmp.f16 } endif

Example

v_div_fixup_legacy_f16 v5, 0, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_vop3_e64.s). Not from an AMD document, and not authored here.

Sources