v_cvt_sr_fp8_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_sr_fp8_f32

Convert from a single-precision float input to an FP8 value with stochastic rounding using seed data from the second input.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1101101011
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 875 in OP rebuilds 0x00000000D76B0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 676, field layout), AMD CDNA 3 (opcode 676, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 875
Identifier 0x00000000D76B0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: N/A (OPR_VGPR, FMT_NUM_FP8)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 32-bit integral data. (OPR_SRC, FMT_NUM_U32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Stochastic rounding. Ignores OMOD and clamp.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Convert from a single-precision float input to an FP8 value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL to determine which byte of the destination to overwrite.

Semantics

prev_mode = ROUND_MODE; ROUND_MODE = ROUND_NEAREST_EVEN; s = sign(S0.f32); e = exponent(S0.f32); m = 23'U(32'U(23'B(mantissa(S0.f32))) + S1[31 : 12].u32); tmp = float32(s, e, m); // Add stochastic value to mantissa, wrap around on overflow if OPSEL[3 : 2].u2 == 2'0U then VGPR[laneId][VDST.u32][7 : 0].fp8 = f32_to_fp8(tmp.f32) elsif OPSEL[3 : 2].u2 == 2'1U then VGPR[laneId][VDST.u32][15 : 8].fp8 = f32_to_fp8(tmp.f32) elsif OPSEL[3 : 2].u2 == 2'2U then VGPR[laneId][VDST.u32][23 : 16].fp8 = f32_to_fp8(tmp.f32) else VGPR[laneId][VDST.u32][31 : 24].fp8 = f32_to_fp8(tmp.f32) endif; // Unwritten bytes of D are preserved. ROUND_MODE = prev_mode

Example

v_cvt_sr_fp8_f32 v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx1170_asm_vop3-fake16.s). Not from an AMD document, and not authored here.

Sources