v_div_fmas_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_div_fmas_f32

Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1000110111
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 567 in OP rebuilds 0x00000000D6370000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 482, field layout), AMD CDNA 3 (opcode 482, field layout), AMD CDNA 2 (opcode 482, field layout), AMD CDNA 1 (opcode 482, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 367, field layout), AMD RDNA 1 (opcode 367, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 567
Identifier 0x00000000D6370000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32-bit single-precision floating point value. (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 32-bit single-precision floating point value. (OPR_SRC, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Input denormals are not flushed but output flushing is allowed. V_DIV_SCALE_F32, V_DIV_FMAS_F32 and V_DIV_FIXUP_F32 are all designed for use in a high precision division macro that utilizes V_RCP_F32 and V_MUL_F32 to compute the approximate result and then applies two steps of the Newton-Raphson method to converge to the quotient. If subnormal terms appear during this calculation then a loss of precision occurs. This loss of precision can be avoided by scaling the inputs and then post-scaling the quotient after Newton-Raphson is applied.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two single-precision float inputs and add a third input using fused multiply add, then scale the exponent of the result by a fixed factor if the vector condition code is set. Store the result into a vector register. This operation is designed for use in floating point division macros and relies on V_DIV_SCALE_F32 to set the vector condition code iff the quotient requires post-scaling.

Semantics

if VCC.u64[laneId] then D0.f32 = 2.0F ** 32 * fma(S0.f32, S1.f32, S2.f32) else D0.f32 = fma(S0.f32, S1.f32, S2.f32) endif

Example

v_div_fmas_f32 v5, s105, s105, s105

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources