v_cvt_u32_u16 GPU Native ISA AMD Vector

Vector Arithmetic

v_cvt_u32_u16

Convert from an unsigned 16-bit integer input to an unsigned 32-bit integer value using zero extension and store the result into a vector register.

Encoding

Binary Layout (AMD CDNA 5)
0111111
31:25
VDST
24:17
unassigned
16
1101011
15:9
SRC0
8:0
 

The ENC_VOP1 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 107 in OP rebuilds 0x7E00D600, an identifier AMD lists for this encoding. Bits marked unassigned have no field in the specification. Not the same in every generation: AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout). The same in AMD RDNA 4.

Format VOP1
Width 32 bits
Opcode 107
Identifier 0x7E00D600

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Unsigned 32-bit integral data. (OPR_VGPR, FMT_NUM_U32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Unsigned 16-bit integral data. (OPR_SRC, FMT_NUM_U16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP1 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_cvt_u32_u16 v5, s1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources