v_cvt_scalef32_sr_pk_fp4_f16 GPU Native ISA AMD Vector

V CVT SCALEF32 SR PK FP4 F16 Vector Arithmetic

v_cvt_scalef32_sr_pk_fp4_f16

Scale a packed 2-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Scale a packed 2-component half-precision float input using the exponent provided by the third single-precision float input, then convert the values to a packed FP4 float value with stochastic rounding using seed data from the second input. Store the result into 8 bits of a vector register using OPSEL[3:2] to determine which byte of the destination to overwrite.

Sources