v_div_fixup_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_div_fixup_f16

Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1001010100
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 596 in OP rebuilds 0x00000000D6540000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 519, field layout), AMD CDNA 3 (opcode 519, field layout), AMD CDNA 2 (opcode 519, field layout), AMD CDNA 1 (opcode 519, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 863, field layout), AMD RDNA 1 (opcode 863, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 596
Identifier 0x00000000D6540000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 16-bit half-precision floating point value. (OPR_VGPR, FMT_NUM_F16)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. (OPR_SRC, FMT_NUM_F16)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. (OPR_SRC, FMT_NUM_F16)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: 16-bit half-precision floating point value. (OPR_SRC, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This operation is the final step of a high precision division macro and handles all exceptional cases of division. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given a half-precision float quotient in the first input, a denominator in the second input and a numerator in the third input, detect and apply corner cases related to division, including divide by zero, NaN inputs and overflow, and modify the quotient accordingly. Generate any invalid, denormal and divide-by-zero exceptions that are a result of the division. Store the modified quotient into a vector register. This operation handles corner cases in a division macro such as divide by zero and NaN inputs. This operation is well defined when the quotient is approximately equal to the numerator divided by the denominator. Other inputs produce a predictable result but may not be mathematically useful.

Semantics

sign_out = (sign(S1.f16) ^ sign(S2.f16)); if isNAN(64'F(S2.f16)) then D0.f16 = 16'F(cvtToQuietNAN(64'F(S2.f16))) elsif isNAN(64'F(S1.f16)) then D0.f16 = 16'F(cvtToQuietNAN(64'F(S1.f16))) elsif ((64'F(S1.f16) == 0.0) && (64'F(S2.f16) == 0.0)) then // 0/0 D0.f16 = 16'F(0xfe00) elsif ((64'F(abs(S1.f16)) == +INF) && (64'F(abs(S2.f16)) == +INF)) then // inf/inf D0.f16 = 16'F(0xfe00) elsif ((64'F(S1.f16) == 0.0) || (64'F(abs(S2.f16)) == +INF)) then // x/0, or inf/y D0.f16 = sign_out ? -INF.f16 : +INF.f16 elsif ((64'F(abs(S1.f16)) == +INF) || (64'F(S2.f16) == 0.0)) then // x/inf, 0/y D0.f16 = sign_out ? -16'0.0 : 16'0.0 else D0.f16 = sign_out ? -abs(S0.f16) : abs(S0.f16) endif

Example

v_div_fixup_f16 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources