v_dual_bitop2_b32 GPU Native ISA AMD Vector

Vector Arithmetic

v_dual_bitop2_b32

Compute a 2-operand generic bitwise operation using a truth table encoded into the instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOPD) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOPD

Operands

  • VDSTY
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)
  • SRCY0
    Read. Simple operands. Covers all operands that are allowed as scalar or vector sources except SRC_LITERAL and SRC_LITERAL64. Data format: 32 bits of arbitrary data. (OPR_SRC_SIMPLE, FMT_NUM_B32)
  • VSRCY1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: 32 bits of arbitrary data. (OPR_VGPR, FMT_NUM_B32)

In AMD's order, as its machine-readable ISA specification lists them for the VOPD3XY encoding (AMD CDNA 5).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Sources