v_dual_sub_f32 GPU Native ISA AMD Vector
Vector Arithmetic
v_dual_sub_f32
Subtract the second floating point input from the first input and store the result into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOPD)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Sources
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.