v_floor_f16 GPU Native ISA AMD Vector
V FLOOR F16 Vector Arithmetic
v_floor_f16
Round the half-precision float input down to previous integer and store the result in floating point format into a vector register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.f16 = trunc(S0.f16);
if ((S0.f16 < 16'0.0) && (S0.f16 != D0.f16)) then
D0.f16 += -16'1.0
endif
Example
v_floor_f16 v5, -1A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 208. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project