v_fma_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_fma_f32 VDST, S0, S1, S2

Per-lane single-precision fused multiply-add.

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1000010011
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 531 in OP rebuilds 0x00000000D6130000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 459, field layout), AMD CDNA 3 (opcode 459, field layout), AMD CDNA 2 (opcode 459, field layout), AMD CDNA 1 (opcode 459, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 331, field layout), AMD RDNA 1 (opcode 331, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 531
Identifier 0x00000000D6130000
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Multiplicand
  • S1
    Multiplier
  • S2
    Addend

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Fused Multiply-Add ↗
equivalent with restrictions
fma (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two single-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.

Semantics

VDST[lane] = round_once(S0[lane].f32 * S1[lane].f32 + S2[lane].f32) for each active lane.

Example

v_fma_f32  v3, v0, v1, v2   // per-lane v3 = v0 * v1 + v2

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources