v_fma_f32 GPU Native ISA AMD Vector

V FMA F32 Vector Arithmetic

v_fma_f32 VDST, S0, S1, S2

Per-lane single-precision fused multiply-add.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Width 32 bits
Execution Unit Vector ALU
Register Classes VGPR

Operands

  • VDST
    Destination VGPR
  • S0
    Multiplicand
  • S1
    Multiplier
  • S2
    Addend

GFX Target Compatibility

TargetSupport
gfx942✅ Supported
gfx1100✅ Supported

Related PTX Concepts

Fused Multiply-Add ↗
equivalent with restrictions
fma (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two single-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.

Semantics

VDST[lane] = round_once(S0[lane].f32 * S1[lane].f32 + S2[lane].f32) for each active lane.

Example

v_fma_f32  v3, v0, v1, v2   // per-lane v3 = v0 * v1 + v2

Original illustrative example, written for this site (not reproduced from a specific AMD document).

Sources