v_fract_f64 GPU Native ISA AMD Vector

V FRACT F64 Vector Arithmetic

v_fract_f64

Compute the fractional portion of a double-precision float input and store the result in floating point format into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

0.5ULP accuracy, denormals are accepted. This is intended to comply with the DX specification of fract where the function behaves like an extension of integer modulus; be aware this may differ from how fract() is defined in other domains. For example: fract(- 1.2) = 0.8 in DX. Obey round mode, result clamped to 0x3fefffffffffffff.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f64 = S0.f64 + -floor(S0.f64)

Example

v_fract_f64 v[5:6], -1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources