v_interp_p2_legacy_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_interp_p2_legacy_f16

Half-precision interpolation.

Encoding

Binary Layout (AMD CDNA 1)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
1001110110
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 1). Opcode 630 in OP rebuilds 0x00000000D2760000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3
Width 64 bits
Opcode 630
Identifier 0x00000000D2760000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F16)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_VGPR, FMT_NUM_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_ATTR, FMT_NUM_F16)
  • SRC2
    Read. N/A Data format: N/A (OPR_SRC_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 1).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_interp_p2_legacy_f16 v5, v2, attr0.w, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx9_asm_vop3_e64.s). Not from an AMD document, and not authored here.

Sources