v_frexp_exp_i32_f64 GPU Native ISA AMD Vector

V FREXP EXP I32 F64 Vector Arithmetic

v_frexp_exp_i32_f64

Extract the exponent of a double-precision float input and store the result as a signed 32-bit integer into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP1) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP1
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

This operation satisfies the invariant S0.f64 = significand * (2 ** exponent). See also V_FREXP_MANT_F64, which returns the significand. See the C library function frexp() for more information.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if ((S0.f64 == +INF) || (S0.f64 == -INF) || isNAN(S0.f64)) then D0.i32 = 0 else D0.i32 = exponent(S0.f64) - 1023 + 1 endif

Example

v_frexp_exp_i32_f64 v5, -1

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources