v_interp_mov_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_interp_mov_f32

Given an attribute specifier and a parameter ID (P0, P10 or P20), load one of the parameter values from the local data share into a vector register.

Encoding

Binary Layout (AMD CDNA 1)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
1001110010
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 1). Opcode 626 in OP rebuilds 0x00000000D2720000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 514), AMD RDNA 1 (opcode 514).

Format VOP3
Width 64 bits
Opcode 626
Identifier 0x00000000D2720000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC1
    Read. N/A Data format: Value can be anything. (OPR_PARAM, FMT_ANY)
  • SRC0
    Read. N/A Data format: Value can be anything. (OPR_ATTR, FMT_ANY)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 1).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_interp_mov_f32 v5, p0, attr0.x

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_vintrp.s). Not from an AMD document, and not authored here.

Sources