v_ldexp_f64 GPU Native ISA AMD Vector
V LDEXP F64 Vector Arithmetic
v_ldexp_f64
Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Compare with the ldexp() function in C.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Description
Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register.
Semantics
D0.f64 = S0.f64 * 2.0 ** S1.i32
Example
v_ldexp_f64 v[5:6], -1, -1A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 361. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project