v_lshl_add_u64 GPU Native ISA AMD Vector

V LSHL ADD U64 Vector Arithmetic

v_lshl_add_u64

Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

The design treats unsupported shift counts as a shift of zero.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given a shift count in the second input, calculate the logical shift left of the first input, then add the third input to the intermediate result, then store the final result into a vector register. For this opcode the shift count must be between 0 and 4, higher shift counts are unsupported.

Semantics

D0.u64 = (S0.u64 << S1.u32[2 : 0].u32) + S2.u64

Sources