v_mad_i32_i16 GPU Native ISA AMD Vector

Vector Arithmetic

v_mad_i32_i16

Multiply two signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the…

Encoding

Binary Layout (AMD CDNA 5)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
1001011010
25:16
CLAMP
15
OPSEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 602 in OP rebuilds 0x00000000D65A0000, an identifier AMD lists for this encoding. Not the same in every generation: AMD CDNA 4 (opcode 498, field layout), AMD CDNA 3 (opcode 498, field layout), AMD CDNA 2 (opcode 498, field layout), AMD CDNA 1 (opcode 498, field layout), AMD RDNA 3.5 (field layout), AMD RDNA 3 (field layout), AMD RDNA 2 (opcode 885, field layout), AMD RDNA 1 (opcode 885, field layout). The same in AMD RDNA 4.

Format VOP3
Width 64 bits
Opcode 602
Identifier 0x00000000D65A0000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: Signed 32-bit integral data. (OPR_VGPR, FMT_NUM_I32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 16-bit integral data. (OPR_SRC, FMT_NUM_I16)
  • SRC1
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 16-bit integral data. (OPR_SRC, FMT_NUM_I16)
  • SRC2
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: Signed 32-bit integral data. (OPR_SRC, FMT_NUM_I32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two signed 16-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the result as a signed 32-bit integer into a vector register.

Semantics

D0.i32 = 32'I(S0.i16) * 32'I(S1.i16) + S2.i32

Example

v_mad_i32_i16 v5, v1, v2, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources