v_mac_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_mac_f16

Multiply two floating point inputs and accumulate the result into the destination register. Implements IEEE rules and non-standard rule for OPSEL.

Encoding

Binary Layout (AMD CDNA 4)
0
31
100011
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 35 in OP rebuilds 0x46000000, an identifier AMD lists for this encoding. The same in the other 3 generations that define it.

Format VOP2
Width 32 bits
Opcode 35
Identifier 0x46000000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F16)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_F16)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Supports round mode, exception flags, saturation.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = S0.f16 * S1.f16 + D0.f16; if OPSEL.u4[3] then D0 = { tmp.f16, D0[15 : 0] } else D0 = { 16'0, tmp.f16 } endif

Example

v_mac_f16 v5, 0, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_vop2.s). Not from an AMD document, and not authored here.

Sources