v_mac_f16 GPU Native ISA AMD Vector
V MAC F16 Vector Arithmetic
v_mac_f16
Multiply two floating point inputs and accumulate the result into the destination register. Implements IEEE rules and non-standard rule for OPSEL.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Supports round mode, exception flags, saturation.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
tmp = S0.f16 * S1.f16 + D0.f16;
if OPSEL.u4[3] then
D0 = { tmp.f16, D0[15 : 0] }
else
D0 = { 16'0, tmp.f16 }
endif
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 178.