v_ldexp_f32 GPU Native ISA AMD Vector
V LDEXP F32 Vector Arithmetic
v_ldexp_f32
Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Description
Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register.
Example
v_ldexp_f32 v5, v1, v2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.
- LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project