v_fmac_legacy_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_fmac_legacy_f32

Multiply two single-precision values and accumulate the result with the destination. Follows DX9 rules where 0.0 times anything produces 0.0.

Also written as v_fmac_dx9_zero_f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 2)
0
31
000110
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD RDNA 2). Opcode 6 in OP rebuilds 0x0C000000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP2
Width 32 bits
Opcode 6
Identifier 0x0C000000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: N/A (OPR_SRC, FMT_NUM_F32)
  • VSRC1
    Read. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: N/A (OPR_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_fmac_legacy_f32 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources