v_ldexp_f16 GPU Native ISA AMD Vector

V LDEXP F16 Vector Arithmetic

v_ldexp_f16

Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Compare with the ldexp() function in C. Note that the S1 has a format of f16 since floating point literal constants are interpreted as 16 bit value for this opcode.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply the first input, a floating point value, by an integral power of 2 specified in the second input, a signed integer value, and store the floating point result into a vector register.

Semantics

D0.f16 = S0.f16 * 16'F(2.0F ** 32'I(S1.i16))

Example

v_ldexp_f16 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources