v_mac_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_mac_f32

Multiply two floating point inputs and accumulate the result into the destination register.

Encoding

Binary Layout (AMD CDNA 2)
0
31
010110
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 2). Opcode 22 in OP rebuilds 0x2C000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 1 (opcode 31). The same in AMD CDNA 1.

Format VOP2
Width 32 bits
Opcode 22
Identifier 0x2C000000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_F32)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_mac_f32 v5, 0, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_vop2.s). Not from an AMD document, and not authored here.

Sources