v_mad_i32_i24 GPU Native ISA AMD Vector

V MAD I32 I24 Vector Arithmetic

v_mad_i32_i24

Multiply two signed 24-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

24-Bit Multiply-Add ↗
equivalent with restrictions
mad24 (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two signed 24-bit integer inputs in the signed 32-bit integer domain, add a signed 32-bit integer value from a third input, and store the result as a signed 32-bit integer into a vector register.

Semantics

D0.i32 = 32'I(S0.i24) * 32'I(S1.i24) + S2.i32

Example

v_mad_i32_i24 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources