24-Bit Multiply-Add Arithmetic
Multiply two 24-bit integer values held in 32-bit registers and add a third 32-bit value.
Vendor-Neutral Definition
d = (a[23:0] * b[23:0]) + c, computed exactly since a 24x24-bit product fits in 48 bits.
⚠️ Cross-vendor mappings describe semantic relationships and are not guaranteed one-to-one compiler
translations.
equivalent with restrictions
Both compute an exact 24x24-bit integer multiply-add in a single instruction.
| Property | NVIDIA PTX | AMDGPU |
|---|---|---|
| Instruction | mad24 | v_mad_i32_i24, v_mad_u32_u24 |
| ISA Layer | Virtual | Native |
| Data Types | - | i32, u32 |
| Version / Target Introduced | PTX ISA 1.0 | gfx1100, gfx1100 |
Important Differences
- Selecting the signed (v_mad_i32_i24) vs. unsigned (v_mad_u32_u24) AMDGPU instruction must match PTX's .hi/.lo and signedness modifiers on mad24.
Source Evidence
- Parallel Thread Execution ISA ↗ - NVIDIA Corporation
- User Guide for AMDGPU Backend ↗ - LLVM Project
Verification method: documentation