v_madmk_f16 GPU Native ISA AMD Vector

V MADMK F16 Vector Arithmetic

v_madmk_f16

Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

This opcode cannot use the VOP3 encoding and cannot use input/output modifiers. Supports round mode, exception flags, saturation.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register. Implements IEEE rules.

Semantics

tmp = S0.f16 * SIMM16.f16 + S1.f16; D0 = { 16'0, tmp.f16 }

Sources