v_madmk_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_madmk_f16

Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2

Operands

  • 1: VGPR
    Vector general-purpose register, one value per lane. Written v1 in the assembler example.
  • 2: VGPR
    Vector general-purpose register, one value per lane. Written v2 in the assembler example.
  • 3: immediate
    Literal value encoded in the instruction. Written 1 in the assembler example.
  • 4: VGPR
    Vector general-purpose register, one value per lane. Written v3 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

This opcode cannot use the VOP3 encoding and cannot use input/output modifiers. Supports round mode, exception flags, saturation.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register. Implements IEEE rules.

Semantics

tmp = S0.f16 * SIMM16.f16 + S1.f16; D0 = { 16'0, tmp.f16 }

Example

v_madmk_f16 v1, v2, 1, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (literal16.s). Not from an AMD document, and not authored here.

Sources