v_max_f32 GPU Native ISA AMD Vector

V MAX F32 Vector Arithmetic

v_max_f32

Select the maximum of two single-precision float inputs and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Maximum ↗
equivalent with restrictions
max (PTX)

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f32))) then D0.f32 = 32'F(cvtToQuietNAN(64'F(S0.f32))) elsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f32))) then D0.f32 = 32'F(cvtToQuietNAN(64'F(S1.f32))) elsif isNAN(64'F(S0.f32)) then D0.f32 = S1.f32 elsif isNAN(64'F(S1.f32)) then D0.f32 = S0.f32 elsif ((64'F(S0.f32) == +0.0) && (64'F(S1.f32) == -0.0)) then D0.f32 = S0.f32 elsif ((64'F(S0.f32) == -0.0) && (64'F(S1.f32) == +0.0)) then D0.f32 = S1.f32 elsif WAVE_MODE.IEEE then D0.f32 = S0.f32 >= S1.f32 ? S0.f32 : S1.f32 else D0.f32 = S0.f32 > S1.f32 ? S0.f32 : S1.f32 endif

Example

v_max_f32 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources