v_max_f16 GPU Native ISA AMD Vector

V MAX F16 Vector Arithmetic

v_max_f16

Select the maximum of two half-precision float inputs and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

IEEE compliant. Supports denormals, round mode, exception flags, saturation.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f16))) then D0.f16 = 16'F(cvtToQuietNAN(64'F(S0.f16))) elsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f16))) then D0.f16 = 16'F(cvtToQuietNAN(64'F(S1.f16))) elsif isNAN(64'F(S0.f16)) then D0.f16 = S1.f16 elsif isNAN(64'F(S1.f16)) then D0.f16 = S0.f16 elsif ((64'F(S0.f16) == +0.0) && (64'F(S1.f16) == -0.0)) then D0.f16 = S0.f16 elsif ((64'F(S0.f16) == -0.0) && (64'F(S1.f16) == +0.0)) then D0.f16 = S1.f16 elsif WAVE_MODE.IEEE then D0.f16 = S0.f16 >= S1.f16 ? S0.f16 : S1.f16 else D0.f16 = S0.f16 > S1.f16 ? S0.f16 : S1.f16 endif

Example

v_max_f16 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources