v_max_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_max_f16

Select the maximum of two half-precision float inputs and store the result into a vector register.

Also written as v_max_num_f16. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 4)
0
31
101101
30:25
VDST
24:17
VSRC1
16:9
SRC0
8:0
 

The ENC_VOP2 layout from AMD's machine-readable ISA specification (AMD CDNA 4). Opcode 45 in OP rebuilds 0x5A000000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 3.5 (opcode 57), AMD RDNA 3 (opcode 57), AMD RDNA 2 (opcode 57), AMD RDNA 1 (opcode 57). The same in AMD CDNA 3, AMD CDNA 2, AMD CDNA 1.

Format VOP2
Width 32 bits
Opcode 45
Identifier 0x5A000000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F16)
  • SRC0
    Read. N/A Data format: N/A (OPR_SRC, FMT_NUM_F16)
  • VSRC1
    Read. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP2 encoding (AMD CDNA 4).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

IEEE compliant. Supports denormals, round mode, exception flags, saturation.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

if (WAVE_MODE.IEEE && isSignalNAN(64'F(S0.f16))) then D0.f16 = 16'F(cvtToQuietNAN(64'F(S0.f16))) elsif (WAVE_MODE.IEEE && isSignalNAN(64'F(S1.f16))) then D0.f16 = 16'F(cvtToQuietNAN(64'F(S1.f16))) elsif isNAN(64'F(S0.f16)) then D0.f16 = S1.f16 elsif isNAN(64'F(S1.f16)) then D0.f16 = S0.f16 elsif ((64'F(S0.f16) == +0.0) && (64'F(S1.f16) == -0.0)) then D0.f16 = S0.f16 elsif ((64'F(S0.f16) == -0.0) && (64'F(S1.f16) == +0.0)) then D0.f16 = S1.f16 elsif WAVE_MODE.IEEE then D0.f16 = S0.f16 >= S1.f16 ? S0.f16 : S1.f16 else D0.f16 = S0.f16 > S1.f16 ? S0.f16 : S1.f16 endif

Example

v_max_f16 v5, -1, v2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources