v_mad_legacy_f16 GPU Native ISA AMD Vector

V MAD LEGACY F16 Vector Arithmetic

v_mad_legacy_f16

Multiply add of FP16 values. Implements IEEE rules and non-standard rule for OPSEL.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Supports round mode, exception flags, saturation. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are written as 0 (this is different from V_MAD_F16). If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

tmp = S0.f16 * S1.f16 + S2.f16; if OPSEL.u4[3] then D0 = { tmp.f16, D0[15 : 0] } else D0 = { 16'0, tmp.f16 } endif

Sources