v_mad_co_u64_u32 GPU Native ISA AMD Vector

Vector Arithmetic

v_mad_co_u64_u32

Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the…

Also written as v_mad_u64_u32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3

Operands

  • 1: VGPR range
    Consecutive vector registers holding a wider value. Written v[3:4] in the assembler example.
  • 2: special register
    Architectural register rather than a general-purpose one. Written null in the assembler example.
  • 3: immediate
    Literal value encoded in the instruction. Written 0xb6db6db7 in the assembler example.
  • 4: VGPR
    Vector general-purpose register, one value per lane. Written v1 in the assembler example.
  • 5: immediate
    Literal value encoded in the instruction. Written 0xffffffffb6db6db7 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply two unsigned integer inputs, add a third unsigned integer input, store the result into a 64-bit vector register and store the overflow/carryout into a scalar mask register.

Example

v_mad_co_u64_u32 v[3:4], null, 0xb6db6db7, v1, 0xffffffffb6db6db7

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13-vop3-literal-canonicalization.s). Not from an AMD document, and not authored here.

Sources