v_madmk_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_madmk_f32

Multiply a floating point input with a literal constant and add a second floating point input, and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2

Operands

  • 1: VGPR
    Vector general-purpose register, one value per lane. Written v5 in the assembler example.
  • 2: immediate
    Literal value encoded in the instruction. Written 0 in the assembler example.
  • 3: immediate
    Literal value encoded in the instruction. Written 0x11213141 in the assembler example.
  • 4: VGPR
    Vector general-purpose register, one value per lane. Written v3 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_madmk_f32 v5, 0, 0x11213141, v3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx7_asm_vop2.s). Not from an AMD document, and not authored here.

Sources