v_interp_p1ll_f16 GPU Native ISA AMD Vector

Vector Arithmetic

v_interp_p1ll_f16

Given a single-precision float I coordinate in a vector register and an attribute specifier, load two half-precision float parameter values from the…

Encoding

Binary Layout (AMD CDNA 1)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110100
31:26
1001110100
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD CDNA 1). Opcode 628 in OP rebuilds 0x00000000D2740000, an identifier AMD lists for this encoding. Not the same in every generation: AMD RDNA 2 (opcode 834), AMD RDNA 1 (opcode 834).

Format VOP3
Width 64 bits
Opcode 628
Identifier 0x00000000D2740000

Operands

  • VDST
    Written. N/A Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC1
    Read. N/A Data format: N/A (OPR_SRC_VGPR, FMT_NUM_F32)
  • SRC0
    Read. N/A Data format: N/A (OPR_ATTR, FMT_NUM_F16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD CDNA 1).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Description

Given a single-precision float I coordinate in a vector register and an attribute specifier, load two half-precision float parameter values from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F16 to complete the operation.

Example

v_interp_p1ll_f16 v5, v2, attr0.w

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx8_asm_vop3_e64.s). Not from an AMD document, and not authored here.

Sources