v_fmaak_f32 GPU Native ISA AMD Vector

V FMAAK F32 Vector Arithmetic

v_fmaak_f32

Multiply two single-precision float inputs and add a literal constant using fused multiply add, and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported
gfx942✅ Supported

This opcode cannot use the VOP3 encoding and cannot use input/output modifiers.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f32 = fma(S0.f32, S1.f32, SIMM32.f32)

Example

v_fmaak_f32 v5, -1, v2, 0xaf123456

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources