v_fma_f16 GPU Native ISA AMD Vector

V FMA F16 Vector Arithmetic

v_fma_f16

Multiply two half-precision float inputs and add a third input using fused multiply add, and store the result into a vector register.

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (VOP3) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format VOP3
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

0.5ULP accuracy, denormals are supported. If OPSEL[3] is 0 Result is written to 16 LSBs of destination VGPR and hi 16 bits are preserved. If OPSEL[3] is 1 Result is written to 16 MSBs of destination VGPR and lo 16 bits are preserved.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Semantics

D0.f16 = fma(S0.f16, S1.f16, S2.f16)

Example

v_fma_f16 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources