v_fma_legacy_f32 GPU Native ISA AMD Vector

Vector Arithmetic

v_fma_legacy_f32

Multiply and add single-precision values. Follows DX9 rules where 0.0 times anything produces 0.0.

Also written as v_fma_dx9_zero_f32. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD RDNA 2)
NEG
63:61
OMOD
60:59
SRC2
58:50
SRC1
49:41
SRC0
40:32
110101
31:26
0101000000
25:16
CLAMP
15
OP_SEL
14:11
ABS
10:8
VDST
7:0
 

The ENC_VOP3 layout from AMD's machine-readable ISA specification (AMD RDNA 2). Opcode 320 in OP rebuilds 0x00000000D5400000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format VOP3
Width 64 bits
Opcode 320
Identifier 0x00000000D5400000

Operands

  • VDST
    Written. Operand must be a vector GPR. Uses an 8-bit operand field. Data format: N/A (OPR_VGPR, FMT_NUM_F32)
  • SRC0
    Read. All operands. Covers all operands that are allowed as scalar or vector sources. Data format: N/A (OPR_SRC, FMT_NUM_F32)
  • SRC1
    Read. Simple operands, plus SRC_LITERAL. Covers all operands that are allowed as scalar or vector sources except for SRC_LDS_DIRECT. Data format: N/A (OPR_SRC_NOLDS, FMT_NUM_F32)
  • SRC2
    Read. Simple operands, plus SRC_LITERAL. Covers all operands that are allowed as scalar or vector sources except for SRC_LDS_DIRECT. Data format: N/A (OPR_SRC_NOLDS, FMT_NUM_F32)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_VOP3 encoding (AMD RDNA 2).

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Vector Arithmetic

Reference

AMDGPU / GFX ISA

Example

v_fma_legacy_f32 v5, v1, v2, s3

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite. Not from an AMD document, and not authored here.

Sources