v_interp_p1lv_f16 GPU Native ISA AMD Vector
V INTERP P1LV F16 Vector Arithmetic
v_interp_p1lv_f16
Given a single-precision float I coordinate in a vector register, a half-precision float P0 value in another vector register, and an attribute…
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (VOP3)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
Per-target GFX compatibility has not yet been verified for this instruction.
Related
More in Vector Arithmetic
Reference
AMDGPU / GFX ISA
Description
Given a single-precision float I coordinate in a vector register, a half-precision float P0 value in another vector register, and an attribute specifier, load a half-precision float parameter value from the local data share, compute the first part of parameter interpolation and store the intermediate result into a vector register. Use V_INTERP_P2_F16 to complete the operation.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.