s_mul_hi_i32 GPU Native ISA AMD Scalar
S MUL HI I32 Scalar Arithmetic
s_mul_hi_i32
Multiply two signed integers and store the high 32 bits of the result into a scalar register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP2)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
D0.i32 = 32'I((64'I(S0.i32) * 64'I(S1.i32)) >> 32U)
Example
s_mul_hi_i32 s0, 0, s2A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 107. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project