s_fmamk_f32 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_fmamk_f32

Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2

Operands

  • 1: SGPR
    Scalar general-purpose register, uniform across the wavefront. Written s0 in the assembler example.
  • 2: SGPR
    Scalar general-purpose register, uniform across the wavefront. Written s0 in the assembler example.
  • 3: immediate
    Literal value encoded in the instruction. Written 0 in the assembler example.
  • 4: SGPR
    Scalar general-purpose register, uniform across the wavefront. Written s0 in the assembler example.

Register classes read from the LLVM assembler example on this page. No source this site uses names these operands, so no names are given.

GFX Target Compatibility

Per-target GFX compatibility has not yet been verified for this instruction.

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Multiply a single-precision float input with a literal constant and add a second single-precision float input using fused multiply add, and store the result into a scalar register.

Example

s_fmamk_f32 s0, s0, 0, s0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sop2.s). Not from an AMD document, and not authored here.

Sources