s_lshl2_add_u32 GPU Native ISA AMD Scalar

S LSHL2 ADD U32 Scalar Arithmetic

s_lshl2_add_u32

Calculate the logical shift left of the first input by 2, then add the second input, store the result into a scalar register and set SCC iff the…

Encoding

Verified bit-level encoding data is not yet available for this instruction. The instruction-format classification below (SOP2) is well-documented and stable; exact per-target opcode/field bit positions have not yet been imported from a verified source.
Format SOP2
Execution Unit

Operands

Operand details have not yet been curated for this instruction.

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Description

Calculate the logical shift left of the first input by 2, then add the second input, store the result into a scalar register and set SCC iff the summation results in an unsigned overflow.

Semantics

tmp = (64'U(S0.u32) << 2U) + 64'U(S1.u32); SCC = tmp >= 0x100000000ULL ? 1'1U : 1'0U; // unsigned overflow. D0.u32 = tmp.u32

Example

s_lshl2_add_u32 s0, 0, s2

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.

Sources