s_clz_i32_u32 GPU Native ISA AMD Scalar
S CLZ I32 U32 Scalar Arithmetic
s_clz_i32_u32
Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Description
Count the number of leading "0" bits before the first "1" in a scalar input and store the result into a scalar register. Store -1 if there are no "1" bits.
Example
s_clz_i32_u32 s5, s1A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
- AMD Machine-Readable GPU ISA Specification ↗ - Advanced Micro Devices, Inc.
- LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project