s_bcnt0_i32_b64 GPU Native ISA AMD Scalar
S BCNT0 I32 B64 Scalar Arithmetic
s_bcnt0_i32_b64
Count the number of "0" bits in a scalar input, store the result into a scalar register and set SCC iff the result is nonzero.
Encoding
Verified bit-level encoding data is not yet available for this instruction.
The instruction-format classification below (SOP1)
is well-documented and stable; exact per-target opcode/field bit positions have not
yet been imported from a verified source.
Operands
Operand details have not yet been curated for this instruction.
GFX Target Compatibility
| Target | Support |
|---|---|
| gfx1100 | ✅ Supported |
Related
More in Scalar Arithmetic
Reference
AMDGPU / GFX ISA
Semantics
tmp = 0;
for i in 0 : 63 do
tmp += S0.u64[i] == 1'0U ? 1 : 0
endfor;
D0.i32 = tmp;
SCC = D0.u64 != 0ULL
Example
s_bcnt0_i32_b64 s0, 0A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx11). Not from an AMD document, and not authored here.
Sources
- User Guide for AMDGPU Backend ↗ - LLVM Project
-
"AMD Instinct MI300" Instruction Set Architecture: Reference Guide ↗
- Advanced Micro Devices, Inc.
Reference Guide, page 117. - LLVM MC assembler tests for AMDGPU (gfx11) ↗ - LLVM Project