s_call_i64 GPU Native ISA AMD Scalar

Scalar Arithmetic

s_call_i64

AMDGPU SOPK scalar instruction operating on i64 data. (Format and name extracted from LLVM's AMDGPU backend source - semantics not yet curated.)

Also written as s_call_b64. AMD's machine-readable ISA specification lists this name for the same instruction.

Encoding

Binary Layout (AMD CDNA 5)
1011
31:28
10100
27:23
SDST
22:16
SIMM16
15:0
 

The ENC_SOPK layout from AMD's machine-readable ISA specification (AMD CDNA 5). Opcode 20 in OP rebuilds 0xBA000000, an identifier AMD lists for this encoding. No other generation in the specification defines this instruction.

Format SOPK
Width 32 bits
Opcode 20
Identifier 0xBA000000

Operands

  • SDST
    Written. All scalar destination operands. Data format: Signed 64-bit integral data. (OPR_SDST, FMT_NUM_I64)
  • SIMM16
    Read. A relative jump offset. Data format: Signed 16-bit integral data. (OPR_LABEL, FMT_NUM_I16)

In AMD's order, as its machine-readable ISA specification lists them for the ENC_SOPK encoding (AMD CDNA 5).

GFX Target Compatibility

TargetSupport
gfx1100✅ Supported

Related PTX Concepts

Function Call ↗
equivalent with restrictions
call (PTX)

Related

More in Scalar Arithmetic

Reference

AMDGPU / GFX ISA

Example

s_call_i64 vcc, 0

A real instruction accepted by the LLVM assembler, taken verbatim from LLVM's own AMDGPU MC test suite (gfx13_asm_sopk.s). Not from an AMD document, and not authored here.

Sources